The present invention relates to diagnosing failures in data processing systems. In particular, the invention relates to built-in, self-test capabilities for data processing system hardware.
Built-in, self-test capabilities have become essential as the design of data processing systems has become more complex. Historically, with simple systems made up of relatively few individual components, each of minimal complexity, testing a data processing system to find a failed component was a simple matter of testing across each component. As system complexity increased with greater levels of integration, access to test points across each component disappeared and the number of components to test to diagnose a data processing system problem skyrocketed.
Even in systems where test points remain, today's high-speed, high-performance data processing systems are difficult to test using an external logic analyzer because of the long lead lines from analyzer to circuit. The long lead lines make accurate testing, at full system clock speed, almost impossible. This is problematic, because some data processing system problems only appear when tested at full system clock speed. In addition, although some useful test information can be obtained with external testing, this becomes very difficult once a data processing system is in the field. Units must be disassembled and protective covers removed to gain access to the test points, increasing the likelihood of inducing further damage to the data processing system. The solution has been to build in an automated capability, such that the system could test itself and report failures.
Built-in, self-test designs generally fall into one of two approaches: a software-based capability or a JTAG boundary scan capability. Both approaches are useful, but have serious drawbacks. Software-based approaches use code stored in the memory used by the central processing unit (CPU) and the CPU itself to test system components and identify and report failures. The major drawback is that if the CPU is not working correctly and is itself part of the problem, the hardware diagnosis process stops or becomes severely limited. In addition, the CPU can not thoroughly test itself or its associated memory because it requires those resources to run the test software.
Boundary scan approaches avoid the working CPU requirement of the software approach by creating a separate test bus to circumvent the communication bus used within the data processing system. Boundary scan is often referred to by the group that began developing a standard for using boundary scans, Joint Test Action Group (JTAG). JTAG is the common name for the IEEE 1149.1 standard, which defines a test bus and defines test ports that components must have to interface with the test bus. As typically implemented, a programmable logic device with the built-in, self-test JTAG firmware is installed in the data processing system and uses the test bus to test some of the data processing system components. Only components designed to interface with the test bus can be tested by the boundary scan method. Such components are commonly referred to JTAG enabled. This is a major limitation on the JTAG boundary scan approach. Many components in a data processing system are not JTAG enabled and, as a result, are not tested by the built-in test, requiring a return to external logic analyzer testing and its attendant problems (if test points are even available). This severely limits the usefulness of the JTAG boundary scan approach in diagnosing data processing system failures. In addition, the JTAG boundary scan approach does not test the communication bus directly, but only through JTAG enabled components, limiting coverage of communication bus testing. For example, a continuity failure at a component not JTAG enabled would not be detected by the boundary scan.
Finally, the JTAG boundary scan test often is not able to operate at full clock speed of the data processing system. As mentioned above, some data processing system problems only appear when tested at full system clock speed. Using the JTAG boundary scan approach makes detection of such high-speed, high-performance system failures impossible.